Electronics And Communication Engineering  

 . Prof. Dr. T.S.Lamba
 . Prof. Dr. Sunil Bhooshan
 . Prof. Dr. D.C.Kulshrestha
 . Dr. G.Singh
 . Dr. D.S. Saini
 . Dr. Pradeep Kumar
 . Dr. Rajiv Kumar
 . Dr. Rohit Sharma
 . Dr. Vinay Kumar
 . Dr. Vivek Sehgal
 . Mr. Alok Joshi
 . Mr. Bhasker Gupta
 . Mr. Jitendra Mohan
 . Ms. Neeru Sharma
 . Ms. Pragya Gupta
 . Mr. Sajai Vir Singh
 . Mr. S.V.R.K Rao
 . Ms. Shruti Jain
 . Mr. Tapan Jain
 . Mr. Mohammad Wajid
 . Mr. Pardeep Garg
 . Mr. Salman Raju Talluri
 . Ms. Vanita Rana
 . Mr. Vipin Balyan
 . Mr.Viranjay Srivastava
 . Mr. Munish Sood
 . Mr. Vikas Hastir
 . Mr. Vinod Kumar

Vipin Balyan

Lecturer

E-mail :balyan.vipin@gmail.com ; balyanvipin@yahoo.co.in

Telephone : (+91) 01792-239355

 

Education:

Pursuing Ph.D in “Efficient Single Code Assignment in OVSF based W-CDMA Wireless Networks”.

M.Tech: Electronics & Networking, LaTrobe University, Melbourne.

B.Tech: Electronics & Communication.

Area of Interest :

Wireless Networks (Ad Hoc Networks), VLSI Design(Power Dissipations in MOS)

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Brief Background :

Biography:
Vipin Balyan received M.Tech Degree in Electronics & Networking from Latrobe University,Melbourne,Australia and B.E Degree with Honours from U.P.Technical University,U.P.He is pursuing Ph.d in Wireless Networks from Jaypee University,Solan.
He joined RK Group of Institutions, Ghaziabad as a Lecturer in the year 2006, and worked for WaveTek Communication Noida as a Network Engineer in the year 2004.

Professional Experience
1. July’2008 – till date: Lecturer, Electronics and Communication Engineering Department, Jaypee University of Informtion Technology, Wakanghat, Solan, India.
2. Oct’2006-July’2008: Lecturer, Electronics and Communication Engineering Department, RKGIT,Ghaziabad,India.

Certifications:

CCNA: Cisco Certified Network Associate(2003-2005)

Projects:

1. UART (Universal Asynchronous Receiver-Transmitter)DESIGN Using
   VHDL.
2. DESIGN OF FUNCTION GENERATOR Using VHDL.
3. DESIGN OF FLOATING POINT ALU Using VHDL.
4. STOP WATCH Using FPGA.
5. Chat Server Using C.

 

Publications

1. Vipin Balyan and Davinder S Saini, Call Elapsed Time and Reduction in Code Blocking for WCDMA Networks, Softcom 2009, Croatia, Sept. 2009.

2. Davinder S Saini, Vipin Balyan, Saurab Kanwar, Pulkit Parikh and Uttam Kumar, A fair multi code OVSF design for 3G and beyond wireless networks, Softcom 2009, Croatia, Sept. 2009.

3. Vipin Balyan,Gunjan Gupta,”Technology Scaling effect on Total Power Dissipation”,National Conference on Emerging Trends in Embedded Technology (ETET-2009) on Feb’14,2009, SGIT,Ghaziabad,India.

4. Vipin Balyan,Gunjan Gupta,”Architecture of Clustered NOC(Network on chip)”,National Conference on Emerging Trends & Technologies(Commune-09),on Apr’16,2009,NIT Kurukshetra, Kurukshetra,India.

5. Vipin Balyan,Gunjan Gupta,”Low Power IA Processor based on 45nm High K-Metal Gate CMOS Technology”, National conference on Emerging Trends in Software & Networking Technologies (ETSNT’09) on Apr’17,2009,AMITY University,Noida,India.

6. Vipin Balyan,Gunjan Gupta,”OVSF Codes W-CDMA”, National Conference on Emerging Trends in Computer Science & Information Technology (afsetconf-09) on Apr’18,2009.Al-Falah School of Engineering & Technology, Faridabad, Haryana.

7. Vipin Balyan,Gunjan Gupta,”Sensing,Analysis and Control of SRAM in Nano Technology”,Emerging Trends in Computer Science & Information Technology (afsetconf-09)on  Apr’18, 2009.Al-Falah School of Engineering & Technology, Faridabad, Haryana.

Conferences Attended:

1. Armstrong, J., Suraweera, H. A, Chai, C., Feramez, M.?Impulse Noise Mitigation Techniques for OFDM Receivers and Their Application in Digital Video Broadcasting? The Mediterranean Journal of Electronics and Communications, vol. 1, no. 1, pp. 1-10.

2. Salim, T., Devlin, J., Whittington, J., Bhatti, M.?An Efficient Serial Distributed Arithmetic Algorithm for FPGA Implementation of Digital Up Conversion?, Complexity, vol. 11, no.1, pp. 24-29. April 2005.

3. Deng, G., Ng, W.?A model-based approach for the development of LMS algorithms? 2005 IEEE International Symposium on Circuits and Systems Proceedings, Kobe, Japan, May 2005.

4. Salim, T., Devlin, J., Whittington, J., ?FPGA Implementation of a Phased Array DBF Using Distributed Arithmetic Method?, IFIP WG 10.5 Conference on Very Large Scale Integration System-On-Chip VLSO-SoC 2005 Proceedings, Perth, Australia, October 2005.

5. Cahill, L., Analysis of the Switching States of Cascaded Generalised Mach-Zehnder Switches? Bragg Gratings, Poling & Photosensitivity/30th Australian Conference on Optical Fibre Technology, Sydney, Australia, July 2005.

 

 

 

 

 

 

 

 

 

 

 

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